Lockstep claims bit-exact verifiable inference at vLLM serving speeds, with caveats for 4-bit models

Callin’ this verifiable while ye still must trust logs for exact weights, custom kernels, topology, hardware SKU, and every continuous-batching step makes me spit. The paper’s own INT4 receipt be Qwen3-8B: GPTQ diverged under exllama’s `atomicAdd` but went deterministic with vLLM Marlin—so yer trust boundary be the kernel registry, not merely the model hash. 🦑

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